trudyniisiТруды НИИСИSRISA Proceedings2225-73493033-6422НИЦ «КУРЧАТОВСКИЙ ИНСТИТУТ» - НИИСИtrudyniisi-22Research ArticleПРОЕКТИРОВАНИЕ И МОДЕЛИРОВАНИЕ СБИСDESIGN AND MODELING OF VLSIГрафовые нейронные сети и их применение при проектировании цифровых СБИСGraph neural networks and their application in the design of digital VLSIЖелудковН. В.ZheludkovN. V.

Москва

nvgel@cs.niisi.ras.ruПетровК. А.PetrovK. A.

Москва

petrovk@cs.niisi.ras.ruФГУ ФНЦ НИИСИ РАНРоссия2022151020251246167Copyright © Желудков Н.В., Петров К.А., 20252025Желудков Н.В., Петров К.А.Zheludkov N.V., Petrov K.A.This work is licensed under a Creative Commons Attribution 4.0 License.https://www.t-niisi.ru/jour/article/view/22

В статье рассматривается метод машинного обучения на графах, представлены архитектуры современных графовых нейронных сетей, а также их применение для решения задач проектирования цифровых СБИС, в особенности при размещении стандартных ячеек на этапе топологического проектирования. Решение данной задачи с помощью методов машинного обучения является актуальной проблемой, так как стандартные алгоритмы размещения, используемые в современных САПР, сталкиваются со сложностями при работе с цифровыми схемами, число логических элементов в которых достигает 106 и более. Это приводит к длительному времени работы и неоптимальности полученных результатов по параметрам занимаемой площади и энергопотребления проектируемой СБИС.

The article discusses the method of machine learning on graphs, presents the architecture of modern graph neural networks, as well as their application for solving digital VLSI design problems, especially in placing standard cells at the layout design stage. The solution of this problem using machine learning methods is an urgent problem, since the standard placement algorithms used in modern CAD systems face difficulties when working with digital circuits, the number of logic elements in which reaches 106 and more. This leads to a long operating time and non-optimality of the results obtained in terms of the occupied area and power consumption of the designed VLSI.

машинное обучениеграфовые нейронные сетиGNNтопологическое проектирование СБИСmachine learninggraph neural networks (GNN)layout design of VLSIReferencesW.L. Hamilton, R. Ying, J. Leskove. Representation Learning on Graphs: Methods and Applications. «Bulletin of the IEEE Computer Society Technical Committee on Data Engineering», Vol. 40 (2017), №3, 52-74.W.L. Hamilton, R. Ying, J. Leskove. Representation Learning on Graphs: Methods and Applications. «Bulletin of the IEEE Computer Society Technical Committee on Data Engineering», Vol. 40 (2017), №3, 52-74.M.M. Bronstein, J. Bruna, Y, LeCun, A.Szlam. Geometric Deep Learning: Going beyond Euclidean data. “IEEE Signal Processing Magazine”, Vol. 34 (2017), №6, 18-42.M.M. Bronstein, J. Bruna, Y, LeCun, A.Szlam. Geometric Deep Learning: Going beyond Euclidean data. “IEEE Signal Processing Magazine”, Vol. 34 (2017), №6, 18-42.T.N. Kipf, M. Welling. Semi-supervised Classification with Graph Convolutional Networks. “5th International Conference on Learning Representations 2017”, France, Toulon, ICLR, 2017, 66-80.T.N. Kipf, M. Welling. Semi-supervised Classification with Graph Convolutional Networks. “5th International Conference on Learning Representations 2017”, France, Toulon, ICLR, 2017, 66-80.W.L. Hamilton. Graph Representation Learning. Synthesis Lectures on Artificial Intelligence and Machine Learning, Vol. 14 (2019), №3, 1-159.W.L. Hamilton. Graph Representation Learning. Synthesis Lectures on Artificial Intelligence and Machine Learning, Vol. 14 (2019), №3, 1-159.G. Huang, J. Hu, Y. He. Machine Learning for Electronic Design Automation: A Survey. “ACM Transactions on Design Automation of Electronic Systems”, Vol. 26 (2021), №5, 1-46.G. Huang, J. Hu, Y. He. Machine Learning for Electronic Design Automation: A Survey. “ACM Transactions on Design Automation of Electronic Systems”, Vol. 26 (2021), №5, 1-46.Y. Zhang, M. Ren, B. Khailany. GRANNITE: Graph neural Network Interference for Transferable Power Estimation. “Design Automation Conference (DAC) 2020”, USA, San Francisco, IEEE, 2020.Y. Zhang, M. Ren, B. Khailany. GRANNITE: Graph neural Network Interference for Transferable Power Estimation. “Design Automation Conference (DAC) 2020”, USA, San Francisco, IEEE, 2020.V. Zhang, M. Ren, B. Keller, B. Khailany. MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. “Design, Automation & Test in Europe Conference & Exhibition, 2021”, France, Grenoble, 2021, IEEE, 2021.V. Zhang, M. Ren, B. Keller, B. Khailany. MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification. “Design, Automation & Test in Europe Conference & Exhibition, 2021”, France, Grenoble, 2021, IEEE, 2021.M. Ren, G. Kokai, W. Turner, T. Ku. ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks, “Design Automation Conference (DAC) 2020”. USA, San Francisco, IEEE, 2020.M. Ren, G. Kokai, W. Turner, T. Ku. ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks, “Design Automation Conference (DAC) 2020”. USA, San Francisco, IEEE, 2020.R. Kirby, S. Godil, R. Roy, B. Catanzaro. CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks. “IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) 2019”, Peru, Cuzco, IEEE, 2019.R. Kirby, S. Godil, R. Roy, B. Catanzaro. CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks. “IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC) 2019”, Peru, Cuzco, IEEE, 2019.Y. Lu, S. Pentapati, S.K. Lim. VLSI Placement Optimization using Graph Neural Networks. “IEEE/ACM International Conference On Computer Aided Design (ICCAD)”, USA, San Diego, 2020.Y. Lu, S. Pentapati, S.K. Lim. VLSI Placement Optimization using Graph Neural Networks. “IEEE/ACM International Conference On Computer Aided Design (ICCAD)”, USA, San Diego, 2020.

The authors declare that there are no conflicts of interest present.