Using the Cosimulation Method in High-Performance Microprocessors Development
Abstract
In the development of high-performance microprocessors, low abstraction level modeling creates a large load on computing machines and takes a lot of time. A simulation method that allows to reduce load on computers and simulation time using a part of the simulated microprocessor in the form of a higher-level abstraction is considered in this article.
About the Authors
A. G. Vorsin
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
A. V. Shumakov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
K. A. Petrov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
P. S. Zubkovskiy
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
References
1. Robert G. Sargen, Verification and validation of simulation model, IEEE 2011.
2. Harry D. Foster, 2018 FPGA Functional Verification Trends, IEEE 2018.
3. Ney Calazans, Edson Moreno, Fabiano Hessel, Vitor Rosa, Fernando Moraes, Everton Carara, From VHDL Register Transfer Level to SystemC Transaction Level Modeling: a Comparative Case Study, IEEE 2003.
4. Maddu Karunaratne, A. Sagahayroon, RTL fault modeling, IEEE 2005.
5. Claudio Gomes, Casper Thule, David Broman, Peter Gorm Larsen, Co-Simulation: A Survey, 2018 ACM Computing Surveys.
6. Fabrice Bellard, QEMU, a Fast and Portable Dynamic Translator, DBPL 2005.
7. IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language, 901-915, IEEE 2013.
Review
For citations:
Vorsin A.G., Shumakov A.V., Petrov K.A., Zubkovskiy P.S. Using the Cosimulation Method in High-Performance Microprocessors Development. МАТЕМАТИЧЕСКОЕ И КОМПЬЮТЕРНОЕ МОДЕЛИРОВАНИЕ СЛОЖНЫХ СИСТЕМ: ТЕОРЕТИЧЕСКИЕ И ПРИКЛАДНЫЕ АСПЕКТЫ. 2022;12(4):68-72. (In Russ.)
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