Estimation of Congestion Map in the VLSI Design of Digital Blocks with Graph Neural Network
Abstract
This paper considers a solution to the problem of estimating the congestion map in the early stages of VLSI layout design of digital blocks by applying a neural network model of machine learning based on a graph neural network. Early prediction of congestion problems will allow the layout engineer to modify design block characteristics such as floorplan, IP-block`s placement and input-output ports to prevent interconnect routing issues at later stages, thereby reducing the number of CAD runs and overall circuit design runtime. The application of graph neural networks allows to take into account additional information about the connections of elements in the netlist for more accurate prediction.
About the Authors
N. V. Zheludkov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
I. M. Karandashev
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
E. S. Kocheva
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
M. K. Saibodalov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
Z. B. Sokhova
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
A. A. Umnova
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
References
1. [Электронный ресурс]. URL: https://theopenroadproject.org/ (дата обращения: 10.11.2023)
2. A.B. Chowdhury, B. Tan, R. Karri, S. Garg. OpenABC-D: A Large-Scale Dataset for Machine Learning Guided Integrated Circuit Synthesis. (2021). ArXiv preprint (2021) arXiv:2110.11292.
3. R. Kirby, S. Godil, R. Roy, B. Catanzaro. Congestionnet: Routing congestion prediction using deep graph neural networks. «2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)», 2019, pp. 217–222.
4. A. Ghose, V. Zhang, Y. Zhang, D. Li, W. Liu, M. Coates. Generalizable cross-graph embedding for GNN-based congestion prediction. «2021 IEEE/ACM International Conference on Computer Aided Design (ICCAD)», 2021, pp. 1–9.
5. P. Velickovic, G. Cucurull, A. Casanova, A. Romero, P. Lio, Y. Bengio. Graph attention networks. ArXiv preprint (2017) arXiv:1710.10903.
6. W.L. Hamilton, Z. Ying, J. Leskovec. Inductive representation learning on large graphs. «Neural Information Processing Systems», 2017.
7. M. Fey, J.E. Lenssen. Fast Graph Representation Learning with PyTorch Geometric. «ICLR Work-shop on Representation Learning on Graphs and Manifolds», 2019.
8. P. Kudva, A. Sullivan, W. Dougherty. Metrics for structural logic synthesis. «IEEE/ACM International Conference on Computer Aided Design», 2002, pp. 551−556.
Review
For citations:
Zheludkov N.V., Karandashev I.M., Kocheva E.S., Saibodalov M.K., Sokhova Z.B., Umnova A.A. Estimation of Congestion Map in the VLSI Design of Digital Blocks with Graph Neural Network. SRISA Proceedings. 2023;13(4):91-96. (In Russ.)
Views:
22
Email this article 