Optimization of Redundancy with Separation of Sensitive Areas for Fault-tolerant System-on-chip
Abstract
This paper describes a modified compared to previous developments method of triple modular redundancy (TMR) with separation of sensitive areas of digital synthesized logic, which allows achieving better indicators in terms of occupied area. A comparison of the characteristics of blocks with TMR developed using different design flow. The results of this work are applicable in the design flow of fault-tolerant systems on a chip and were used in the development of a test chip using 28 nm technology node.
About the Authors
P. Chernyakov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
N. Zheludkov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
M. Ladnushkin
ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
A. Antonov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
V. Lazarev
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
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Review
For citations:
Chernyakov P., Zheludkov N., Ladnushkin M., Antonov A., Lazarev V. Optimization of Redundancy with Separation of Sensitive Areas for Fault-tolerant System-on-chip. SRISA Proceedings. 2024;14(3):9-14. (In Russ.)
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