Fault Tolerance Evaluation of IP-Block Topology at Different Stages of Combinational Logic Synthesis
Abstract
The analysis of the fault stability of the obtained schemes with a real topological assessment is represented. Fault toleranсе evaluation of the resulting circuit using a sigmoidal function is proposed. This function can be used to compare different circuits, and also used to find the optimal circuits of a given logical function in heuristic and machine learning algorithms.
About the Authors
E. K. Emin
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
K. A. Petrov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
V. V. Azarov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
A. P. Skorobogatov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
A. A. Antonov
ФГУ ФНЦ НИИСИ РАН
Russian Federation
Russian Federation
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Review
For citations:
Emin E.K., Petrov K.A., Azarov V.V., Skorobogatov A.P., Antonov A.A. Fault Tolerance Evaluation of IP-Block Topology at Different Stages of Combinational Logic Synthesis. SRISA Proceedings. 2023;13(4):75-79. (In Russ.)
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