Sensitivity of the Potential Distribution in the Channel of Silicon GAA Nanotransistors to the Anomalous Behavior of the Metal Gate Grain
Abstract
The influence of the anomalous grain size of the metal gate of a silicon field-effect GAA nanotransistor with cylindrical geometry on the potential distribution in its working area is discussed. Based on the analytical solution of the 2D Poisson equation, an analytical model has been developed to analyze the sensitivity of the potential distribution of silicon field GAA nanotransistors to the abnormal behavior of the metal gate grain. The variations of the potential distribution in transistors with short and thin working areas with a length from 25 to 11 nm are quantitatively analyzed. The dependence of the potential perturbation on the location of the abnormal grain on the gate is shown. The linear dependence of the amplitude of the disturbance on the magnitude of the output operation jump is established. A mathematical model of the fluctuation of the potential distribution has been developed, including variations in the unevenness of the boundaries of the anomalous grain area. The nonuniformity of the boundaries of the anomalous region makes an additional contribution to the transformation of the potential. With approximately the same deformations of the boundaries, the contribution of this mechanism is not significant. With a significant asymmetry of the boundaries, the contribution can exceed 10% of the perturbation generated by the ideal ring.
References
1. International Roadmap for Devices and Systems (IRDS), More Moore. 2017. Available online: https://irds.ieee.org/roadmap-2017 (accessed on 15 September 2022).
2. J.S. Yoon, T. Rim, J. Kim, K. Kim, C.K. Baek, Y.H. Jeong. Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors // “Appl. Phys. Lett.”, (2015), V. 106, 103507
3. D. Nagy, G. Indalecio, A.J. Garcia-Loureiro, M.A. Elmessary, K. Kalna, N. Seoane. FinFET versus gate-all-around nanowire FET: performance, scaling, and variability. // “IEEE Journal of the Electron Devices Society”, (2018), V. 6, 332-40.
4. M. Onobajo, J. Silva-Martinez. Analog circuit design for process variation-resilient systems-on-achip. Dordrecht: Springer, 2012.
5. M.M. Tehranipoor, U. Guin, D. Forte. Counterfeit integrated circuits: Detection and Avoidance. Springer, 2015.
6. I. Ferain, C.A. Colinge, J. Colinge. Multigate transistors as the future of classical metal–oxide– semiconductor field-effect transistors // “Nature”, (2011), V. 479, 310–316.
7. K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshwari, W.K. Shih, S. Sivakumar, G. Taylor, P. VanDerVoorn, K. Zawadzki. Managing process variation in Intel’s 45nm CMOS technology // “Intel Technology Journal”, (2008), V. 12, 93-109.
8. J. A. Croon, W. Sansen, H.E. Maes. Matching properties of deep sub-micron MOS transistors, Springer, 2005
9. S.K. Saha. Modeling process variability in scaled CMOS technology. // “IEEE Design Test of Computers”, (2010), V. 27, 8–16.
10. K. K Young. Analysis of conduction in fully depleted SOI MOSFETs // “IEEE Trans. Electron Devices”, (1989), V. 36, No. 3, 504-506.
11. Н.В. Масальский. Влияние зернистости металлического затвора кремниевых конических GAA нанотранзисторв на флуктуации порогового напряжения // “Труды НИИСИ РАН”, (2023), Т. 60, № 6, 387-393
12. Н.В. Масальский. Моделирование ВАХ ультратонких КНИ КМОП нанотранзисторов с полностью охватывающим затвором // “Микроэлектроника”, (2021), Т. 60, № 6, 387-393
Review
For citations:
Masalsky N. Sensitivity of the Potential Distribution in the Channel of Silicon GAA Nanotransistors to the Anomalous Behavior of the Metal Gate Grain. SRISA Proceedings. 2024;14(4):47-53. (In Russ.)
Views:
18
Email this article 