This paper examines the evolution of the neural network module architecture of the Mirera Digital Educational Platform in connection with the expanding range of applied artificial intelligence models. It is shown that the original LLM-oriented orchestrator core did not allow models of other modalities to be integrated without substantial reworking. A universal multimodal architecture is described, including a service manager abstraction based on a unified contract, configurable request-processing chains, and a unified stream of output artifacts. Examples of integrations are presented. It is shown that the proposed architecture enables the integration of new model types without modifying the router core and provides a basis for the further development of multimodal educational scenarios.

The paper presents a comparative analysis of five multi-agent debate architectures of large language models in a decision-support task related to evaluating the quality of educational tests. The study aims to identify how communication topology affects decision quality, computational cost, latency, and robustness. A unified experimental setting was used to compare a baseline, linear, cyclic, cross, and model-elimination architecture. The corpus comprised 60 tests from four school disciplines split into correct and errors subsets, while the model ensemble included Qwen 2.5 72B Instruct, Grok 4.1 Fast, and Gemma 4 26B-A4B IT. The main evaluation metrics were macro-F1 for detecting problematic questions, macro-MAE for the numerical assessment of test quality, and token usage, cost per test, and response time for operational comparison. The results show that the model-elimination architecture achieved the highest observed macro-F1 within the experiment, while the baseline architecture remained superior in macro-MAE and cost-efficiency. The study also demonstrates that some debate architectures are highly sensitive to the type of test and that increasing the number of rounds does not guarantee sustained quality improvement. The findings support treating debate architecture as a controllable design parameter of decision-support systems rather than as a neutral implementation detail.

This article considers the problem of creating a stable input power supply node for a printed circuit board (PCB) of a microprocessor system connected to a power source via a long cable. It is shown that under these conditions, the use of expensive, large-capacity ceramic capacitors without taking damping into account can lead to an unstable transient process, since the cable inductance, together with the input capacitance, form a resonant circuit with a sufficiently high Q factor. An approach to constructing an input power supply node is proposed that ensures damping of resonant processes without excessive voltage drop and overheating, shunting of high-frequency current components, and localization of interference. The main idea of this approach is to use the ESR of the storage input capacitor as a means of resonance damping, and to compensate for the effect of series inductance with small-value ceramic capacitors. It is shown that a similar principle is unacceptable in local decoupling circuits of microcircuits. Recommendations are provided for selecting the range of equivalent series resistance values, the nominal values of input capacitors, and the placement of components on the PCB.

An IP block has been developed that provides the reception of streaming data from an external analog-to-digital converter (ADC) over the SPI interface. A distinctive feature of this block is that the ADC acts as the master, generating the clock signal and controlling data exchange on the SPI bus. Interfacing with an ADC of this type requires implementing the SPI controller in slave mode. The proposed IP block consists of an SPI slave controller, a configuration register block, and a direct memory access (DMA) module. The use of DMA minimizes the involvement of the central processor: the sequence of data received from the ADC is accumulated in an internal buffer, after which it is transferred as a burst to a specified address in system memory without software intervention. The block supports operation with ADCs of 10, 12, 14, and 16 bits in resolution; single and circular DMA modes are also implemented, along with an interrupt system triggered by buffer-fill events.

This paper addresses the integration of a PCI Express controller developed at NIISI RAS with high-speed transceivers of Xilinx UltraScale+ FPGAs. The initial implementation used a fixed x16 transceiver configuration regardless of the actual PCI Express link width, leading to excessive hardware resource utilization when operating in narrower-lane modes. A scalable interface block is proposed that automatically selects the appropriate transceiver configuration based on the required PCIe link width. The developed solution supports Endpoint and Root Complex modes, Gen1–Gen3 data rates, and x1, x2, x4, x8, x16 lane widths. To verify functionality, a parameterizable testbench script has been developed, allowing simulation of any supported configuration with a single command without manual project restructuring. Experimental evaluation was performed on the Xilinx Virtex UltraScale+ VCU128 board. The obtained results demonstrate hardware savings for narrower-lane configurations and confirm the effectiveness of the proposed automated verification approach.

The automation of selecting and constructing SRM (Svenska Rotor Maskiner) screw-rotor profiles is considered. The study deals with the classical case of screw rotors having a constant helix lead along the rotor length and an unchanged cross-sectional profile from the suction port to the discharge port. A method is proposed for the parametric synthesis of a base profile, i.e., an initial profile serving as the starting point for its subsequent shape optimization and satisfying the technical specification and the conditions of geometric feasibility (hereinafter referred to as an admissible base profile, or simply a base profile). The search over nine design parameters is performed by a genetic algorithm with built-in control of geometric and kinematic feasibility and parallel evaluation of individuals. The correctness of the synthesized geometry is confirmed by an independent computation of the paired-cavity volume by two methods. For a test specification of an associated-petroleum-gas compression stage, a base profile was obtained within several generations with a maximum partial error of specification matching of about 4.8%; the discrepancy between the two volume-computation methods did not exceed 0.5%. The method is implemented as an end-to-end automated pipeline with export of profile coordinates for construction in CAD systems.

The article describes a technique for converting tables from a text file format to an electronic spreadsheet format using the report generator of the Automated Control System of SRISA.