Glitch-free dynamic phase retuning unit in high-speed DDR PHY clocking circuits

Abstract

This paper discusses a modification of the Clock Phase Adjustment unit within the digital interface block of a DDR PHY, designed for generating and adjusting clock signals in the transmit and receive paths. The relevance of this task is driven by the increasing demands on the timing stability of high-speed interfaces and the necessity to calibrate phase relationships without interrupting path operation. In the original architecture, changing a delay involves a procedure for updating the controlled delay line and must be accompanied by a pause in the operation of the corresponding section of the clock path. The proposed modification transitions the Clock Phase Adjustment Block unit to a circuit with a shadow adjustment path, where the new delay value is prepared in an inactive branch, and switching to the updated configuration is performed via glitch-safe clock control logic. This solution eliminates the need to stop the operational clock signal, reduces the risk of synchronization disruption, and enables seamless phase retuning during system operation.