Parametrization of the transceiver connection block of a PCI Express controller for FPGA resource optimization and verification automation

This paper addresses the integration of a PCI Express controller developed at NIISI RAS with high-speed transceivers of Xilinx UltraScale+ FPGAs. The initial implementation used a fixed x16 transceiver configuration regardless of the actual PCI Express link width, leading to excessive hardware resource utilization when operating in narrower-lane modes. A scalable interface block is proposed that automatically selects the appropriate transceiver configuration based on the required PCIe link width. The developed solution supports Endpoint and Root Complex modes, Gen1–Gen3 data rates, and x1, x2, x4, x8, x16 lane widths. To verify functionality, a parameterizable testbench script has been developed, allowing simulation of any supported configuration with a single command without manual project restructuring. Experimental evaluation was performed on the Xilinx Virtex UltraScale+ VCU128 board. The obtained results demonstrate hardware savings for narrower-lane configurations and confirm the effectiveness of the proposed automated verification approach.

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