Determining current threats to information security for a certain object of assessment, as a rule, should be carried out according to the Methodology for Assessing Security Threats, approved on February 5, 2021 as a methodological document of the FSTEC of Russia. This article shows that, provided that the main element of the assessment object, e.g., OS, (which implements the main mechanisms of the subsystem for protecting information from unauthorized access) and for which there is a security profile introduced in the established order, the list of typical security threats can also be obtained from the analysis of this document. Comparison of information security threats obtained from the security profile of operating systems of type “B” of the 4^th security class, with a list of information security threats obtained from the FSTEC of Russia Database based on the expert method, after optimizing this list and the exclusion of repeated threats from it, shows that the remaining threats are in certain correspondence with the threats from the security profile with some detail on their implementation.

The article discusses the possibility of using hardware performance counters, commonly used in the creating of system execution profiles, to identify potential security threats to critically important systems and complexes. The authors have ported an open Performance Application Programming Interface (PAPI), which is used to manage hardware counters.

The goal of this manuscript is to provide an overview of the basic low level cryptographic operations at the heart of modern cryptographic protocols. We consider the examples of some widely used operations of cryptographic hashing, encryption and the digital signature calculation.

The article considers the architecture of a typical Internet of Things system, identifies a set of requirements for components of a typical Internet of Things system, and based on these requirements, the requirements for the development and maintenance of systems implementing the Internet of Things paradigm are formulated.

The article describes the project of a software platform designed for HIL simulation and digital twins based on the Baget PLC. The approach proposed by the authors provide a full set of tool for HIL simulation and a wide application range of the platform.

The article describes the application of the distributed simulation concept HLA (High Level Architecture) when developing HIL simulation stands for automated process control systems. A brief overview of the history of HLA, the advantages and disadvantages of this standard in relation to the task at hand is given, and the functionality provided by the HLA standard is analyzed. The author assessed the feasibility of using the HLA concept when developing tools for HIL simulation stands based on the PLC Baget.

Due to high risks of using foreign-made industry automation solutions in critical infrastructure, importance of locally produced solutions can’t be overestimated. The article describes a generic architecture of an automated process control system based on programmable logic controller, operating system, developer tools and other software developed by NIISI. Proposed solutions are based on international industry standards.

The article contains a brief overview of the main stages of the development of the C programming language since its creation. The existing standards of this language are considered. Close attention is paid to the new standard of the C language – C23. Its advantages and disadvantages are highlighted.

The analysis of the fault stability of the obtained schemes with a real topological assessment is represented. Fault toleranсе evaluation of the resulting circuit using a sigmoidal function is proposed. This function can be used to compare different circuits, and also used to find the optimal circuits of a given logical function in heuristic and machine learning algorithms.

The possibility of using the method of automated selection of optimal parameters in the process of designing IP-blocks to optimize their energy consumption is investigated. The I/O interface unit of the processor and coprocessor communication and the unit of integer multiplication-division of 64-bit numbers were used as objects of research. The results obtained allow us to conclude that it is expedient to use the investigated method in the design route of IP blocks.

To increase the performance of universal microprocessors of MIPS-like architecture, NIISI RAS developed a specialized coprocessor that allows accelerating operations with complex and real numbers of single and double precision. The article presents the results of using a 128-bit vector coprocessor for the image filtering task. Using the example of two vectorization options, the increase in the efficiency of calculations when solving this problem is show

This paper considers a solution to the problem of estimating the congestion map in the early stages of VLSI layout design of digital blocks by applying a neural network model of machine learning based on a graph neural network. Early prediction of congestion problems will allow the layout engineer to modify design block characteristics such as floorplan, IP-block`s placement and input-output ports to prevent interconnect routing issues at later stages, thereby reducing the number of CAD runs and overall circuit design runtime. The application of graph neural networks allows to take into account additional information about the connections of elements in the netlist for more accurate prediction.

The article provides an overview about the using machine learning methods in various areas of functional verification. We consider the use of machine learning in "pre-silicon" verification, precisely in simulation-based verification and Universal Verification Methodology. Then we discuss the field of "post-silicon" verification. The main decision was made in conclusion about the main areas of machine learning applications, as well as possible future directions of research.

The probability of a miss in a random test of the cache system depends mainly on memory layout. It makes it possible to limit the number of active cache lines, thereby forcing the load on the cache. Enumerating memory areas in the test generator allows one to reduce auxiliary actions in the test that are not directly related to the target of testing. Estimates of the probability of a miss in caches of the first and second levels under various conditions serve to select parameters for generating effective tests.

The influence of the grain size of a metal gate on the fluctuation of the threshold voltage of a silicon field GAA nanotransistor is discussed. Based on Pelgor's theorem, a method of reliable estimation of threshold voltage fluctuations has been developed. Pelgorm coefficients were obtained in the range of transistor gate lengths from 11 to 25 nm and average grain sizes from 3 to 10 nm. The relative errors between the model values of the standard deviation of the threshold voltage and the data obtained from 3D modeling are in almost 95% of cases below 5%.

GPUs, built from a large number of relatively simple an similar execution units and having high peak performance, have been used long time in high-performance computing as accelerators. Nowday there are GPUs that were specially designed for use in supercomputer centers, and not as graphics processors.
Current trends in their development are presented.

A model of the process of forming evidence based on the use of critical thinking was constructed and analyzed. An analysis of methods for using critical reasoning in the scientific process is carried out. The analyzed model contributes to the study of cognitive evolution.

During the trial operation of educational platforms, there may be difficulties and needs for innovations or fixes that were not noticeable during development and testing. Timely improvements and changes contribute to improving the user experience and reduce the amount of effort spent on performing inconvenient actions in the system, which allows you to better concentrate on completing basic tasks, such as teaching or studying. This article describes the problems that users have encountered while using the set of modules of the digital educational platform of Mirera, and methods for solving them.