The methods used in implementing information security tools for the Baget real-time operating system (RTOS) are considered. The access control model is based on control of user access to commands. The methods for identifying and authenticating users are described. The user interface for executing commands, the software interface for registering user command handlers, and the RTOS configuration tools are also described.

The open62541 freely distributed library implementing the OPC UA protocol has been ported to the environment of the domestic real-time operating system of the Baget family. The article provides an overview of the basic concepts of OPC UA, lists the functional capabilities of the ported version of the library, describes a model task, and provides an analysis of key fragments of its code.

The article discusses the use of the ARINC 653 standard principles as a basis for developing applications in the languages of the IEC 61131-3 standard for execution on a programmable logic controller (PLC) running under the RTOS Baget 3.6. The article discusses the scheme for using a multi-threaded approach to implementing application tasks, when each task operates with its own period and priority, independently of other application tasks and driver programs servicing input-output devices. The article also discusses the principles of generating diagnostic messages.

A comparative analysis of the time spent on designing digital IP cores using automated selection of input parameters in CAD and without automated selection is carried out. Two IP cores were used for the analysis: Integer Multiplication/Division and the I/O interface. The result of the analysis showed the advantage of an automated system for selecting CAD input parameters in terms of reducing the time spent on searching for their optimal values.

For a large crossbar resistor array, local recording of information into the selected variable resistor (that is, changing the conductivity of this resistor) faces difficulties associated with a limited number of control signals - voltages on the conductors of the structure. Since the number of conductors is significantly less than the number of resistors, when voltage is applied to the target resistor, voltages arise on many non-target resistors. The corresponding changes in the conductivities of non-target resistors must be compensated. The paper considers the recording procedure using high-frequency harmonic signals and with addressing control by varying the resistances of the connection resistors. Based on the analysis using the model of a simple resistor element, the possibility of point recording of information into a resistor array, that is a local change in the conductivity matrix, is shown. The conditions ensuring the feasibility and convenience of such a procedure are discussed.

The possibility of using a special Lambert function to simulate the volt-ampere characteristics of silicon field-effect transistors is investigated. An analytical model of a silicon field-effect GAA nanotransistor with a cylindrical geometry of the working area has been developed. At the same time, in the transistor model formulated within the framework of charge separation, the integral expression for the transistor current is replaced by an analytical one using the Lambert function. The calculation results are compared with the simulation results obtained using a widely used software and technology modeling environment. The final formulation of the model is characterized by the following advantages: it is analytical, adequate and compact. High accuracy is achieved with minimal computational cost. This makes it possible to use the considered approach in design tools and the search for an initial approximation for three-dimensional applied technological modeling.

The influence of the anomalous grain size of the metal gate of a silicon field-effect GAA nanotransistor with cylindrical geometry on the potential distribution in its working area is discussed. Based on the analytical solution of the 2D Poisson equation, an analytical model has been developed to analyze the sensitivity of the potential distribution of silicon field GAA nanotransistors to the abnormal behavior of the metal gate grain. The variations of the potential distribution in transistors with short and thin working areas with a length from 25 to 11 nm are quantitatively analyzed. The dependence of the potential perturbation on the location of the abnormal grain on the gate is shown. The linear dependence of the amplitude of the disturbance on the magnitude of the output operation jump is established. A mathematical model of the fluctuation of the potential distribution has been developed, including variations in the unevenness of the boundaries of the anomalous grain area. The nonuniformity of the boundaries of the anomalous region makes an additional contribution to the transformation of the potential. With approximately the same deformations of the boundaries, the contribution of this mechanism is not significant. With a significant asymmetry of the boundaries, the contribution can exceed 10% of the perturbation generated by the ideal ring.

The paper discusses the development and design methodology of an organic package with BGA (Ball Grid Array) ball leads with two crystals connected by high-speed interfaces. The features of the chiplet topology are described. The main technologies and stages of development are considered. A review of the developments of foreign analogues was carried out.

Different groups of tests are used to compare the performance of computing clusters. The Laptest comprehensive performance testing program was developed to determine the efficiency parameters of the computing cluster systems with a large number of cores. Due to the high energy consumption of supercomputers, energy efficiency of executing tasks has become one of the most important features of computing systems. The article describes the implementation of energy consumption estimation in the Laptest program.

The hypothesis about the possibility of assessing the impact of the program source code on the computing system power consumption is tested in the work. The authors proposed an algorithm for assessing the program code energy efficiency based on the studied optimization methods. The software tool prototype as an extension for Visual Studio Code implementing the presented algorithm was developed. Experimental results on the study of various ways to improve the program code energy efficiency, as well as the results of testing the developed algorithm operability are presented.

Simulators are popular tools for studying the supercomputer workload managers as complex multiuser systems. The paper formulates requirements for a simulator of a HPC system that includes geographically distributed supercomputers. Compliance with the stated requirements can be ensured by implementing an external simulator control interface. An analysis of the characteristics of modern HPC workload manager simulators is presented from the stated requirements point of view. The architecture of a workload manager simulator with external control interface is proposed. The first results of using the Elytra simulator, which implements the proposed architecture, are considered.

Nowadays, it is impossible to imagine the progress in science and technology without computer modeling on high-performance computing machines. This paper provides an overview of modern processors of various architectures for HPC.

This paper contains detailed proof of the Uspensky-Rice theorem. Basic definitions related to computable functions are introduced. The computing model of an unlimited register machine is used. The presentation is of thorough and elementary nature.